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FSAM50SM60A
April 3, 2006
FSAM50SM60A
SPMTM (Smart Power Module)
General Description
FSAM50SM60A is an advanced smart power module (SPM) that Fairchild has newly developed and designed to provide very compact and low cost, yet high performance ac motor drives mainly targeting medium speed low-power inverter-driven application like air conditioners. It combines optimized circuit protection and drive matched to low-loss IGBTs. Highly effective short-circuit current detection/ protection is realized through the use of advanced current sensing IGBT chips that allow continuous monitoring of the IGBTs current. System reliability is further enhanced by the built-in over-temperature and integrated under-voltage lock-out protection. The high speed built-in HVIC provides opto-coupler-less IGBT gate driving capability that further reduce the overall size of the inverter system design. In addition the incorporated HVIC facilitates the use of singlesupply drive topology enabling the FSAM50SM60A to be driven by only one drive supply voltage without negative bias. Inverter current sensing application can be achieved due to the devided nagative dc terminals.
Features
* UL Certified No. E209204 * 600V-50A 3-phase IGBT inverter bridge including control ICs for gate driving and protection * Divided negative dc-link terminals for inverter current sensing applications * Single-grounded power supply due to built-in HVIC * Typical switching frequency of 5kHz * Built-in thermistor for over-temperature monitoring * Isolation rating of 2500Vrms/min. * Very low leakage current due to using DBC (Direct Bonded Copper) substrate * Adjustable current protection level by varying series resistor value with sense-IGBTs
Applications
* AC 100V ~ 253V three-phase inverter drive for small power ac motor drives * Home appliances applications like air conditioners drive system
External View
Top View Bottom View
60mm
31mm
Fig. 1.
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Integrated Power Functions
* 600V-50A IGBT inverter for three-phase DC/AC power conversion (Please refer to Fig. 3)
Integrated Drive, Protection and System Control Functions
* For inverter high-side IGBTs: Gate drive circuit, High voltage isolated high-speed level shifting Control circuit under-voltage (UV) protection Note) Available bootstrap circuit example is given in Figs. 13 and 14. * For inverter low-side IGBTs: Gate drive circuit, Short circuit protection (SC) Control supply circuit under-voltage (UV) protection * Temperature Monitoring: System over-temperature monitoring using built-in thermistor Note) Available temperature monitoring circuit is given in Fig. 14. * Fault signaling: Corresponding to a SC fault (Low-side IGBTs) or a UV fault (Low-side control supply circuit) * Input interface: 5V CMOS/LSTTL compatible, Schmitt trigger input
Pin Configuration
Top View
(1)VCC(L) (2)COM(L) (3)IN(UL) (4)IN(VL) (5)IN(WL) (6)COM(L) (7)VFO (8)CFOD (9)CSC (10)RSC (11)IN(UH) (12)VCC(UH) (13)VB(U) (14)VS(U) (15)INV(H) (16)COM(H) (17)VCC(VH) (18)VB(V) (19)VS(V) (20)IN(WH) (21)VCC(WH) (22)VB(W) (23)VS(W)
(24)VTH (25)RTH (26)NU (27)NV (28)NW
(29)U
Case Temperature(TC) Detecting Point
(30)V
(31)W DBC Substrate (32)P
Fig. 2.
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Pin Descriptions
Pin Number 1 Pin Name VCC(L) Pin Description Low-side Common Bias Voltage for IC and IGBTs Driving
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
COM(L) IN(UL) IN(VL) IN(WL) COM(L) VFO CFOD CSC RSC IN(UH) VCC(UH) VB(U) VS(U) IN(VH) COM(H) VCC(VH) VB(V) VS(V) IN(WH) VCC(WH) VB(W) VS(W) VTH RTH NU NV NW U V W P
Low-side Common Supply Ground Signal Input Terminal for Low-side U Phase Signal Input Terminal for Low-side V Phase Signal Input Terminal for Low-side W Phase Low-side Common Supply Ground Fault Output Capacitor for Fault Output Duration Time Selection Capacitor (Low-pass Filter) for Short-Circuit current Detection Input Resistor for Short-circuit Current Detection Signal Input for High-side U Phase High-side Bias Voltage for U Phase IC High-side Bias Voltage for U Phase IGBT Driving High-side Bias Voltage Ground for U Phase IGBT Driving Signal Input for High-side V Phase High-side Common Supply Ground High-side Bias Voltage for V Phase IC High-side Bias Voltage for V Phase IGBT Driving High-side Bias Voltage Ground for V Phase IGBT Driving Signal Input for High-side W Phase High-side Bias Voltage for W Phase IC High-side Bias Voltage for W Phase IGBT Driving High-side Bias Voltage Ground for W Phase IGBT Driving Thermistor Bias Voltage Series Resistor for the Use of Thermistor (Temperature Detection) Negative DC-Link Input Terminal for U Phase Negative DC-Link Input Terminal for V Phase Negative DC-Link Input Terminal for W Phase Output for U Phase Output for V Phase Output for W Phase Positive DC-Link Input
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Internal Equivalent Circuit and Input/Output Pins
Bottom View
(22) VB(W) (21) VCC(WH) P (32)
VB VCC COM IN OUT VS
W (31)
(20) IN(WH) (23) VS(W) (18) VB(V) (17) VCC(VH) (16) COM(H) (15) IN(VH) (19) VS(V) (13) VB(U) (12) VCC(UH) (11) IN(UH) (14) VS(U)
VB VCC COM IN OUT VS
V (30)
VB VCC COM IN OUT VS
U (29)
(10) RSC (9) CSC (8) CFOD (7) VFO (6) COM(L) (5) IN(WL) (4) IN(VL) (3) IN(UL) (2) COM(L) (1) VCC(L)
C(SC) OUT(WL) C(FOD) VFO IN(WL) OUT(VL) IN(VL) IN(UL) COM(L) VCC
NU (26) RTH (25) THERMISTOR VTH (24) NV (27) NW (28)
OUT(UL)
Note 1. Inverter low-side is composed of three sense-IGBTs including freewheeling diodes for each IGBT and one control IC which has gate driving, current sensing and protection functions. 2. Inverter power side is composed of four inverter dc-link input pins and three inverter output pins. 3. Inverter high-side is composed of three normal-IGBTs including freewheeling diodes and three drive ICs for each IGBT.
Fig. 3.
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Absolute Maximum Ratings (TJ = 25C,
Inverter Part
Item Symbol VDC
Unless Otherwise Specified)
Supply Voltage Supply Voltage (Surge) Collector-emitter Voltage Each IGBT Collector Current Each IGBT Collector Current Each IGBT Collector Current (Peak) Collector Dissipation Operating Junction Temperature
Condition Applied to DC - Link
Rating 450
Unit V
VPN(Surge) VCES IC IC ICP PC TJ
Applied between P- N TC = 25C TC = 100C TC = 25C , Under 1ms pulse width TC = 25C per One Chip (Note 1)
500 600 50 25 100 100 -20 ~ 125
V V A A A W C
Note 1. It would be recommended that the average junction temperature should be limited to TJ 125C (@TC 100C) in order to guarantee safe operation.
Control Part
Item Control Supply Voltage Symbol Condition VCC Applied between VCC(UH), VCC(VH), VCC(WH) COM(H), VCC(L) - COM(L) Rating 20 Unit V
High-side Control Bias Voltage Input Signal Voltage Fault Output Supply Voltage Fault Output Current Current Sensing Input Voltage
VBS VIN VFO IFO VSC
Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) VS(W) Applied between IN(UH), IN(VH), IN(WH) - COM(H) IN(UL), IN(VL), IN(WL) - COM(L) Applied between VFO - COM(L) Sink Current at VFO Pin Applied between CSC - COM(L)
20 -0.3 ~ VCC+0.3 -0.3 ~ VCC+0.3 5 -0.3 ~ VCC+0.3
V V V mA V
Total System
Item Self Protection Supply Voltage Limit (Short Circuit Protection Capability) Symbol Condition VPN(PROT) Applied to DC - Link, VCC = VBS = 13.5 ~ 16.5V TJ = 125C, Non-repetitive, less than 6s Rating 400 Unit V
Module Case Operation Temperature Storage Temperature Isolation Voltage
TC TSTG VISO
Note Fig. 2 60Hz, Sinusoidal, AC 1 minute, Connection Pins to Heat-sink Plate
-20 ~ 100 -20 ~ 125 2500
C C Vrms
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Absolute Maximum Ratings
Thermal Resistance
Item Junction to Case Thermal Resistance Symbol Rth(j-c)Q Condition Inverter IGBT part (per 1/6 module) Min. Typ. Max. 1.0 Unit C/W
Rth(j-c)F Rth(c-f)
Inverter FWDi part (per 1/6 module) Ceramic Substrate (per 1 Module) Thermal Grease Applied (Note 3)
-
-
1.5 0.06
C/W C/W
Contact Thermal Resistance
Note 2. For the measurement point of case temperature(TC), please refer to Fig. 2. 3. The thickness of thermal grease should not be more than 100um.
Package Marking and Ordering Information
Device Marking Device Package Real Size Tape Width Quantity
FSAM50SM60A
FSAM50SM60A
SPM32-CA
-
-
8
Electrical Characteristics
Inverter Part (TJ = 25C, Unless Otherwise Specified)
Item Collector - emitter Saturation Voltage Symbol VCE(SAT) VCC = VBS = 15V VIN = 0V Condition IC = 50A, TJ = 25C Min. Typ. Max. 2.4 Unit V
FWDi Forward Voltage Switching Times
VFM tON tC(ON) tOFF tC(OFF) trr
VIN = 5V
IC = 50A, TJ = 25C
-
0.69 0.32 1.32 0.46 0.10 -
2.1 250
V
s s s s s A
VPN = 300V, VCC = VBS = 15V IC = 50A, TJ = 25C VIN = 5V 0V, Inductive Load (High-Low Side) (Note 4) VCE = VCES, TJ = 25C
Collector - emitter Leakage Current
ICES
Note 4. tON and tOFF include the propagation delay time of the internal drive IC. tC(ON) and tC(OFF) are the switching time of IGBT itself under the given gate driving condition internally. For the detailed information, please see Fig. 4.
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
t rr VCE
100% IC
IC
IC
VCE
V IN t ON
VIN(ON)
V IN
t C(ON)
90% IC 10% IC 10% VCE
t OFF
V IN(OFF)
tC(OFF)
10% VCE 10% I C
(a) Turn-on
(b) Turn-off
Fig. 4. Switching Time Definition
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Electrical Characteristics Control Part
(TJ = 25C, Unless Otherwise Specified)
Item Symbol Quiescent VCC Supply Cur- IQCCL VCC = 15V rent IN(UL, VL, WL) = 5V
Condition VCC(L) - COM(L)
Min. -
Typ. Max. Unit 26 mA
IQCCH Quiescent VBS Supply Current Fault Output Voltage Short-Circuit Trip Level Sensing Voltage of IGBT Current Supply Circuit UnderVoltage Protection IQBS VFOH VFOL VSC(ref) VSEN UVCCD UVCCR UVBSD UVBSR Fault Output Pulse Width ON Threshold Voltage OFF Threshold Voltage ON Threshold Voltage OFF Threshold Voltage Resistance of Thermistor tFOD VIN(ON) VIN(OFF) VIN(ON) VIN(OFF) RTH
VCC = 15V IN(UH, VH, WH) = 5V VBS = 15V IN(UH, VH, WH) = 5V
VCC(UH), VCC(VH), VCC(WH) COM(H) VB(U) - VS(U), VB(V) -VS(V), VB(W) - VS(W)
4.5 0.45 0.45 11.5 12 7.3 8.6 1.4
-
130 420 1.1
uA uA V V V V V V V V ms V V V V k k
VSC = 0V, VFO Circuit: 4.7k to 5V Pull-up VSC = 1V, VFO Circuit: 4.7k to 5V Pull-up VCC = 15V (Note 5) RSC = 40 , RSU = RSV = RSW = 0 and IC = 75A (Fig. 6) Detection Level Reset Level Detection Level Reset Level CFOD = 33nF (Note 6) High-Side Low-Side Applied between IN(UH), IN(VH), IN(WH) - COM(H) Applied between IN(UL), IN(VL), IN(WL) - COM(L)
0.51 0.56 0.51 0.56 12 12.5 9.0 10.3 1.8 50 3.4 12.5 13 10.8 12 2.0 0.8 0.8 -
3.0 3.0 -
@ TTH = 25C (Note Fig. 6) (Note 7) @ TTH = 100C (Note Fig. 6) (Note 7)
Note: 5. Short-circuit current protection is functioning only at the low-sides. It would be recommended that the value of the external sensing resistor (RSC) should be selected around 40 in order to make the SC trip-level of about 75A at the shunt resistors (RSU,RSV,RSW) of 0 . For the detailed information about the relationship between the external sensing resistor (RSC) and the shunt resistors (RSU,RSV,RSW), please see Fig. 6. 6. The fault-out pulse width tFOD depends on the capacitance value of CFOD according to the following approximate equation : CFOD = 18.3 x 10-6 x tFOD[F] 7. TTH is the temperature of thermistor itself. To know case temperature (TC), please make the experiment considering your application.
Recommended Operating Conditions
Item Symbol Condition Values Min. Typ. 300 Max. 400 Unit
Supply Voltage Control Supply Voltage High-side Bias Voltage Blanking Time for Preventing Arm-short PWM Input Signal Input ON Threshold Voltage Input OFF Threshold Voltage
VPN VCC VBS tdead fPWM VIN(ON) VIN(OFF)
Applied between P - NU, NV, NW Applied between VCC(UH), VCC(VH), VCC(WH) COM(H), VCC(L) - COM(L) Applied between VB(U) - VS(U), VB(V) - VS(V), VB(W) - VS(W) For Each Input Signal TC 100C, TJ 125C Applied between IN(UH), IN(VH), IN(WH) COM(H), IN(UL), IN(VL), IN(WL) - COM(L) Applied between IN(UH), IN(VH), IN(WH) COM(H), IN(UL), IN(VL), IN(WL) - COM(L)
V V V us kHz V V
13.5 13.5 3.5 -
15 15 5 0 ~ 0.65 4 ~ 5.5
16.5 16.5 -
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
R -T C urve
70 60 50
Resistance [k]
40 30 20 10 0 20 30 40 50 60 70 80 90 100 110 120 130
T em perature T T H [ ]
Fig. 5. R-T Curve of The Built-in Thermistor
80
60
Rsc[ ]
40
20
0 0 .0 0 0
0 .0 0 5
0 .0 1 0
0 .0 1 5 R su ,R sv ,R sw [ ]
0 .0 2 0
0 .0 2 5
0 .0 3 0
Fig. 6. RSC Variation by change of Shunt Resistors ( RSU, RSV, RSW) for Short-Circuit Protection @ Current Trip Level 50A, @ Current Trip Level 75A
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Mechanical Characteristics and Ratings
Item Condition Limits Min. 8 Typ. 10 Max. 12 Units
Mounting Torque DBC Flatness Weight
Mounting Screw: M4 (Note 8 and 9)
Recommended 10Kg*cm Recommended 0.98N*m Note Fig.7
Kg*cm N*m
m
0.78 0 -
0.98 32
1.17 +120 -
g
(+) (+)
(+)
Fig. 7. Flatness Measurement Position of The DBC Substrate
Note: 8. Do not make over torque or mounting screws. Much mounting torque may cause ceramic cracks and bolts and Al heat-fin destruction. 9. Avoid one side tightening stress. Fig.8 shows the recommended torque order for mounting screws. Uneven mounting can cause the SPM ceramic substrate to be damaged.
2 1
Fig. 8. Mounting Screws Torque Order (1 2)
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Time Charts of SPMs Protective Function
Input Signal Internal IGBT Gate-Emitter Voltage Control Supply Voltage P3 P5 UV detect P1 P2 UV reset P6
Output Current Fault Output Signal P4
P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : Fault signal generation P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current
Fig. 9. Under-Voltage Protection (Low-side)
Input Signal Internal IGBT Gate-Emitter Voltage Control Supply Voltage VBS P3 P5 UV detect P1 P2 UV reset P6
Output Current Fault Output Signal
P4
P1 : Normal operation - IGBT ON and conducting current P2 : Under voltage detection P3 : IGBT gate interrupt P4 : No fault signal P5 : Under voltage reset P6 : Normal operation - IGBT ON and conducting current
Fig. 10. Under-Voltage Protection (High-side)
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
P5 Input Signal Internal IGBT Gate-Emitter Voltage
SC Detection
P6
P1 P4 Output Current P2
SC Reference Voltage (0.5V) RC Filter Delay
P7
Sensing Voltage
Fault Output Signal
P3
P8
P1 : Normal operation - IGBT ON and conducting currents P2 : Short-circuit current detection P3 : IGBT gate interrupt / Fault signal generation P4 : IGBT is slowly turned off P5 : IGBT OFF signal P6 : IGBT ON signal - but IGBT cannot be turned on during the fault-output activation P7 : IGBT OFF state P8 : Fault-output reset and normal operation start
Fig. 11. Short-circuit Current Protection (Low-side Operation only)
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
5V-Line
SPM
RPF = 4.7k 100 RPL = 2k RPH= 4.7k IN(UH) , IN(VH) , IN(WH) IN(UL) , IN (VL) , IN(WL) VFO CPF = 1nF CPL = 0.47nF CPH= 1.2nF COM
CPU
100 100 1nF
Note: 1) It would be recommended that by-pass capacitors for the gating input signals, IN(UL), IN(VL), IN(WL), IN(UH), IN(VH) and IN(WH) should be placed on the SPM pins and on the both sides of CPU and SPM for the fault output signal, VFO, as close as possible. 2) The logic input is compatible with standard CMOS or LSTTL outputs. 3) RPLCPL/RPHCPH/RPFCPF coupling at each SPM input is recommended in order to prevent input/output signals' oscillation and it should be as close as possible to each of SPM pins.
Fig. 12. Recommended CPU I/O Interface Circuit
These Values depend on PW M Control Algorithm R E(H) 15V-Line
One-Leg D iagram of FSAM50SM60A
RBS
D BS
Vcc VB HO
P
47uF
0.1uF
IN
COM VS
Vcc
Inverter Output
OUT
470uF
1uF
IN COM
N
Note: 1) It would be recommended that the bootstrap diode, DBS, has soft and fast recovery characteristics. 2) The bootstrap resistor (RBS) should be 3 times greater than RE(H). The recommended value of RE(H) is 5.6, but it can be increased up to 20 for a slower dv/dt of high-side. 3) The ceramic capacitor placed between VCC-COM should be over 1F and mounted as close to the pins of the SPM as possible.
Fig. 13. Recommended Bootstrap Operation Circuit and Parameters
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
15V line
RE(WH) RE(VH) RE(UH) RBS DBS
(22) VB(W) (21) VCC(WH) P (32)
5V line VB VCC COM IN
RS Gating WH
RPH CPH RBS
OUT VS
W (31)
CBS
CBSC
(20) IN(WH) (23) VS(W)
DBS
(18) VB(V) (17) VCC(VH)
VB VCC COM IN OUT VS
V (30)
RS Gating VH
RPH CBS CPH CBSC
(16) COM(H) (15) IN(VH) (19) VS(V)
M
CDCS Vdc
C P U
RBS RPH
DBS
(13) VB(U) (12) VCC(UH)
VB VCC COM IN OUT VS
U (29)
RS Gating UH
CBS CPH 5V line RF RPL RPL RPL RPF CSC RSC
CBSC
(11) IN(UH) (14) VS(U)
(10) RSC
RCSC CFOD
(9) CSC (8) CFOD (7) VFO (6) COM(L)
C(SC) OUT(WL) C(FOD) VFO IN(WL) OUT(VL) IN(VL) IN(UL) COM(L) VCC
NU (26) VTH (24) THERMISTOR RTH (25) NV (27) NW (28)
RS Fault RS Gating WH Gating VH Gating UH RS RS CBPF
RSW
(5) IN(WL) (4) IN(VL) (3) IN(UL) (2) COM(L)
RSV
CPL CPL CPL CPF
(1) VCC(L)
OUT(UL) RSU 5V line
CSP15
CSPC15
RTH
CSPC05
CSP05
Temp. Monitoring W-Phase Current V-Phase Current U-Phase Current
CFW CFV CFU
RFW RFV RFU
Note: 1) RPLCPL/RPHCPH /RPFCPF coupling at each SPM input is recommended in order to prevent input signals' oscillation and it should be as close as possible to each SPM input pin. 2) By virtue of integrating an application specific type HVIC inside the SPM, direct coupling to CPU terminals without any opto-coupler or transformer isolation is possible. 3) VFO output is open collector type. This signal line should be pulled up to the positive side of the 5V power supply with approximately 4.7k resistance. Please refer to Fig. 12. 4) CSP15 of around 7 times larger than bootstrap capacitor CBS is recommended. 5) VFO output pulse width should be determined by connecting an external capacitor(CFOD) between CFOD(pin8) and COM(L)(pin2). (Example : if CFOD = 33 nF, then tFO = 1.8 ms (typ.)) Please refer to the note 6 for calculation method. 6) Each input signal line should be pulled up to the 5V power supply with approximately 4.7k (at high side input) or 2k (at low side input) resistance (other RC coupling circuits at each input may be needed depending on the PWM control scheme used and on the wiring impedance of the system's printed circuit board). Approximately a 0.22~2nF by-pass capacitor should be used across each power supply connection terminals. 7) To prevent errors of the protection function, the wiring around RSC, RF and CSC should be as short as possible. 8) In the short-circuit protection circuit, please select the RFCSC time constant in the range 3~4 s. 9) Each capacitor should be mounted as close to the pins of the SPM as possible. 10)To prevent surge destruction, the wiring between the smoothing capacitor and the P&N pins should be as short as possible. The use of a high frequency noninductive capacitor of around 0.1~0.22 F between the P&N pins is recommended. 11)Relays are used at almost every systems of electrical equipments of home appliances. In these cases, there should be sufficient distance between the CPU and the relays. It is recommended that the distance be 5cm at least.
Fig. 14. Application Circuit
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
FSAM50SM60A
Detailed Package Outline Drawings
SPM32-CA
28x2.00 0.30=(56.0) (2.00) 2.00 0.30 MAX1.05 0.60 0.10 0.40 MAX1.00 0.60 0.10 0.40
28.0 0.30
#23 #1
O4.30
31.0 0.50
13.6 0.30
#32
#24
19.860.30 53.0 0.30 60.0 0.50
7.20 0.5 12.30 0.5
3x7.62 0.30=(22.86) 11.0 0.30 3x4.0 0.30=(12.0 ) 2.00 0.30
(10.14)
MAX8.20
MAX1.00
0.80 1.300.10
0.80 1.300.10 MAX2.50
0.40 0.600.10 MAX1.60
MAX3.20
(3.50)
(3.70)
Dimmensions in Millimeters
(c)2006 Fairchild Semiconductor Corporation
April 3, 2006
36.05 0.50
(34.80)
5.5) (2.5~
0.70 -0.05
+0.10
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Preliminary
First Production
No Identification Needed
Full Production
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Not In Production
This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only.
Rev. I18

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